`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:31:09 04/28/2014 
// Design Name: 
// Module Name:    Frame1 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Frame2(
	output 		reg	[7:0] 	color,		
	input					[10:0]	hcounter, vcounter,										
	input 				clk , clk_5Hz, blank		
				);
	
	parameter	GGh=160, GGv=100,	
					RPh=270, RPv=300;	

					
	
	reg	[1:0]		cc;				
	reg	[1:0]		f;
	reg 	[15:0]	addr;
	wire				data;
	
	always@(posedge clk_5Hz)										
			begin 
				if(f<3)
					f<=f+1;
				else					
					f<=0;
			end		
			
	F_ROM_2 U2(clk ,addr, data);	
	
	always@(hcounter, vcounter)
		begin 
			if (blank==0)
				begin
////////////////////////////////GAME OVER////////////////////////////////				
					if (((hcounter-GGh)<327)&&((hcounter-GGh)>=0)&&((vcounter-GGv)<50)&&((vcounter-GGv)>=0))
						begin
							cc<=2'b00;
							addr<=(vcounter-GGv)*327+hcounter-GGh;
						end	

////////////////////////////////REPLAY//////////////////////////////////					
					else if (((hcounter-RPh)<112)&&((hcounter-RPh)>=0)&&((vcounter-RPv)<30)&&((vcounter-RPv)>=0))
						begin
							if (f<2)
								begin
									cc<=2'b01;
									addr<=(vcounter-RPv)*112+hcounter-RPh+16350;
								end
							else 
								begin
									cc<=2'b10;
									addr<=(vcounter-RPv)*112+hcounter-RPh+16350;
								end								
						end
/////////////////////////////////////////////////////////////////////////	
					else 
						begin							
							addr<=0;
						end	
				end
			else
				begin
					addr<=0;
				end
		end
		
		always@(posedge clk)		
			begin
				case (cc)
				2'b00:	
					begin
						color<=data?8'b00000000:8'b11100001;	//game over color
					end
				2'b01:	
					begin
						color<=data?8'b00000000:8'b00011111;	//replay color 1
					end
				2'b10:	
					begin
						color<=data?8'b00000000:8'b11100011;	//replaycolor 2
					end
				2'b11:	
					begin
						color<=data?8'b00000000:8'b00000000;	//not defined
					end
				endcase
			end	
endmodule
